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| HT9172 DTMF Receiver Technical Document * Tools Information * FAQs * Application Note Features * Operating voltage: 2.5V~5.5V * Minimal external component requirements * No external filter required * Low standby current in power down mode) * Excellent performance * Tristate data output for MCU interface * 3.58MHz crystal or ceramic resonator oscillator * 1633Hz can be inhibited by the INH pin * 18-pin DIP/SOP packaging General Description The HT9172 is a Dual Tone Multi Frequency (DTMF) receiver device which includes an integrated digital decoder and band split filter functions as well as power-down and inhibit mode operations. The device uses digital counting techniques to detect and decode the full range of 16 DTMF tone pairs into a 4-bit code output. Highly accurate switched capacitor filters are utilised to divide the DTMF dual tone frequencies into low and high group signals. An integrated dial tone rejection circuit is provided to eliminate the need for pre-filtering. Block Diagram PW DN X2 X1 3 .5 8 M H z C ry s ta l O s c illa to r B ia s C ir c u it V re f G e n e ra to r S te e r in g C o n tr o l C ir c u it VREF R T /G T EST DV DVB VP VN GS L o w G ro u p F ilte r OPA P r e - F ilte r H ig h G r o u p F ilte r F re q u e n c y D e te c to r Code D e te c to r L a tc h & O u tp u t B u ffe r D0 D1 D2 D3 IN H OE Rev. 1.00 1 March 30, 2006 HT9172 Pin Assignment VP 1 2 3 4 5 6 7 8 9 VN GS VREF IN H PW DN X1 X2 VSS 18 17 16 15 14 13 12 11 10 VDD R T /G T EST DV D3 D2 D1 D0 OE H T9172 1 8 D IP -A /S O P -A Pin Description Pin Name VP VN GS VREEF X1 X2 PWDN INH VSS OE I/O I I O O I O I I 3/4 I oscillator VREF Internal Connection Operational Amplifier Description Operational amplifier non-inverting input Operational amplifier inverting input Operational amplifier output terminal Reference voltage output, normally VDD/2 The system oscillator consists of an inverter, a bias resistor and the required on-chip load capacitor. A standard 3.579545MHz crystal connected to the X1 and X2 terminals implements the oscillator function. Active high. This enables the device to go into its power down mode and inhibits the oscillator. This pin input is pulled low internally. Active high. This inhibits the detection of tones representing characters A, B, C and D. This pin input is pulled low internally. Negative power supply, ground D0~D3 output enable, active high Received data output terminals OE=H: Output enable OE=L: High impedance Data valid output. When the device has received a valid DTMF tone, this line will go high; otherwise it remains low. Early steering output - see Functional Description Tone acquisition time and release time can be set through connection with external resistor and capacitor. Positive power supply, 2.5V~5.5V for normal operation CMOS IN Pull-low CMOS IN Pull-low 3/4 CMOS IN Pull-high CMOS OUT Tristate D0~D3 O DV EST RT/GT VDD O O I/O 3/4 CMOS OUT CMOS OUT CMOS IN/OUT 3/4 Rev. 1.00 2 March 30, 2006 HT9172 Approximate Internal Connection Circuits O P E R A T IO N A L A M P L IF IE R VREF X1 VN VP VOPA V+ O S C IL L A T O R X2 C M O S IN P u ll- h ig h EN CMOS OUT T r is ta te GS OPA 20pF 10M 10pF CMOS OUT C M O S IN /O U T C M O S IN P u ll- lo w Absolute Maximum Ratings Supply Voltage ..............................VSS-0.3V to VSS+6V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol VDD IDD ISTB VIL VIH IIL IIH ROE RPL RIN IOH IOL fOSC Parameter Operating Voltage Operating Current Standby Current Input Low Voltage Input High Voltage Input Low Current Input High Current Pull-high Resistance (OE) Pull-low Resistance (INH, PWDN) Input Impedance (VN, VP) Source Current (D0~D3, EST, DV) Sink Current (D0~D3, EST, DV) System Frequency Test Conditions VDD 3/4 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Conditions 3/4 3/4 VPWDN=VDD, (Not include PWDN pull-low current) 3/4 3/4 VVP=VVN=0V VVP=VVN=5V VOE=0V VINH=5.0V, VPWDN=5.0V 3/4 VOUT =4.5V VOUT =0.5V Crystal=3.5795MHz Min. 2.5 3/4 3/4 3/4 4.0 3/4 3/4 70 150 3/4 -0.4 1.0 3.5759 Typ. 5 3 1 3/4 3/4 3/4 3/4 110 250 10 -0.8 2.5 3.5795 Max. 5.5 7 5 1.0 3/4 0.1 0.1 160 375 3/4 3/4 3/4 3.5831 Ta=25C Unit V mA mA V V mA mA kW kW MW mA mA MHz Rev. 1.00 3 March 30, 2006 HT9172 A.C. Characteristics Symbol DTMF Signal 3V Input Signal Level 5V Twist Accept Limit (Positive) Twist Accept Limit (Negative) Dial Tone Tolerance Noise Tolerance Third Tone Tolerance Frequency Deviation Acceptance Frequency Deviation Rejection tPU Power Up Time (See Figure 4.) 5V 5V 5V 5V 5V 5V 5V 5V -36 -29 3/4 3/4 3/4 3/4 3/4 3/4 3.5 3/4 3/4 VSS<(VVP,VVN) Gain Setting Amplifier RIN IIN VOS PSRR CMRR AVO fT VOUT RL CL VCM Input Resistance Input Leakage Current Offset Voltage Power Supply Rejection Common Mode Rejection Open Loop Gain Gain Band Width Output Voltage Swing Load Resistance (GS) Load Capacitance (GS) Common Mode Range 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 10 0.1 25 60 60 65 1.5 4.5 50 100 3.0 MW mA mV dB dB dB MHz VPP kW pF VPP Steering Control tDP tDA tACC tREJ tIA tIR tPDO tPDV tDOV tDDO tEDO Tone Present Detection Time Tone Absent Detection Time Acceptable Tone Duration Rejected Tone Duration Acceptable Inter-digit Pause Rejected Inter-digit Pause Propagation Delay (RT/GT to DO) Propagation Delay (RT/GT to DV) Output Data Set Up (DO to DV) Disable Delay (OE to DO) Enable Delay (OE to DO) 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 11 4 3/4 3/4 3/4 3/4 8 12 4.5 300 50 ms ms ms ms ms ms ms ms ms ns ns Note: DO=D0~D3 Rev. 1.00 4 March 30, 2006 HT9172 V 1 2 3 100kW 5 3 .5 7 9 5 4 5 M H z 7 8 20pF 20pF 9 6 4 18 17 16 15 14 13 12 11 10 300kW DD Tone 0 .1 m F 100kW VP VN GS VREF IN H PW DN X1 X2 VSS VDD R T /G T EST DV D3 D2 D1 D0 OE H T9172 0 .1 m F 0 .1 m F Figure 1. Test Circuit Functional Description Overview The HT9172 tone decoder consists of three band pass filters and two digital decode circuits to convert a DTMF tone into a digital code output. The device contains an operational amplifier to adjust the input signal level as shown in Figure 2. (a ) S ta n d a r d In p u t C ir c u it C V i When the input signal is recognized as an effective DTMF tone, the DV line will go high, and the corresponding DTMF tone code will be generated. Steering Control Circuit The steering control circuit is used to measure the effective signal duration and for protecting against valid signal drop out. This is achieved using an analog delay which is implemented using an external RC time-constant, controlled by the output line EST. The timing diagram is shown in Figure 3. The EST pin is normally low and will pull the RT/GT pin low via the external RC network. When a valid tone input is detected, the EST pin will go high, which will in turn pull the RT/GT pin high through the RC network. When the voltage on RT/GT rises from 0 to VTRT, which is 2.35V for a 5V power supply, the input signal is effective, and the corresponding code will be generated by the code detector. After D0~D3 have been latched, DV will go high. When the voltage on RT/GT falls from VDD to VTRT, i.e. when there is no input tone, the DV output will go low, and D0~D3 will maintain their present data until a next valid tone input is produced. By selecting suitable external RC values, the minimum acceptable input tone duration, tACC, and the minimum acceptable inter-tone rejection, tIR, can be set. The values of the external RC components, can be chosen using the following formula. Also refer to Figure 5 for details. tACC=tDP+tGTP; tIR=tDA+tGTA; where tACC: Tone duration acceptable time tDP: EST output delay time (L(R)H) tGTP: Tone present time tIR: Inter-digit pause rejection time R1 VP VN H T9172 RF GS VREF (b ) D iffe r e n tia l In p u t C ir c u it C1 V V i1 i2 R1 R2 R3 R4 R5 VP VN C2 H T9172 GS VREF Figure 2. Amplifier Input Application Circuits The pre-filter is a band rejection filter which will reject frequencies between 350Hz to 400Hz. The low group filter, filters the low group frequency signal output whereas the high group filter, filters the high group frequency signal output. Each filter output is followed by a zero-crossing detector with incorporates hysteresis. When the signal amplitude at the output exceeds a specified level, it is transferred to a full swing logic signal. Rev. 1.00 5 March 30, 2006 HT9172 Timing Diagrams tR Tone tD P EJ t IA Tone n tD P t IR Tone n+1 tD A tD P EST tA V CC R T /G T TRT tP D 0~D 3 Tone C ode n1 DO tG Tone C ode n tD OV TP tG TA Tone C ode n+1 tP DV tP DV DV tD OE DO tE DO Figure 3. Steering Timing Tone Tone PW DN EST tP U Figure 4. Power-up Timing Rev. 1.00 6 March 30, 2006 HT9172 (a) Fundamental circuit: tGTP = R C Ln (VDD / (VDD - VTRT)) tGTA = R C Ln (VDD / VTRT) V VDD H T9172 C R T /G T EST R H T9172 C R T /G T EST D1 R1 R2 DD (c) tGTP > tGTA : tGTP = R1 C Ln (VDD / (VDD - VTRT)) tGTA = (R1 // R2) C Ln (VDD / VTRT) V VDD DD (b) tGTP < tGTA : tGTP = (R1 // R2) C Ln (VDD - VTRT)) tGTA = R1 C Ln (VDD / VTRT) V VDD H T9172 C R T /G T EST D1 R1 R2 DD Figure 5. Steering Time Adjustment Circuits DTMF Dialing Matrix CO L1 CO L2 ROW 1 ROW 2 ROW 3 ROW 4 7 8 9 C # D 0 * 4 5 6 B 1 2 3 A CO L3 CO L4 DTMF Data Output Table Low Group (Hz) 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 3/4 Note: Z High impedance; Rev. 1.00 High Group (Hz) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 3/4 ANY Any digit 7 March 30, 2006 Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY OE H H H H H H H H H H H H H H H H L D3 L L L L L L L H H H H H H H H L Z D2 L L L H H H H L L L L H H H H L Z D1 L H H L L H H L L H H L L H H L Z D0 H L H L H L H L H L H L H L H L Z HT9172 Data Output The data outputs, D0~D3, are tristate outputs. When the OE input is low, the D0~D3 data outputs, will be in a high impedance condition. Application Circuits Application Circuit 1 V 1 2 3 100kW 5 6 7 X 't a l 9 C1 C2 VSS 8 4 VP VN GS VREF IN H PW DN X1 X2 VSS H T9172 VDD R T /G T EST DV D3 D2 D1 D0 OE 18 17 16 15 14 13 12 11 10 T o o th e r d e v ic e 300kW DD DTM F 0 .1 m F 100kW 0 .1 m F 0 .1 m F T o o th e r d e v ic e Note: Xtal = 3.579545MHz crystal C1 = C2 @ 20pF Xtal = 3.58MHz ceramic resonator C1 = C2 @ 39pF Application Circuit 2 V 0 .1 m F DTM F 0 .1 m F R2 R3 R4 5 T o o th e r d e v ic e 6 7 8 9 VSS R1 180pF 2 3 4 R5 1 VP VN GS VREF IN H PW DN X1 X2 VSS H T9172 D3 D2 D1 D0 OE DV VDD R T /G T EST 18 17 16 300kW 15 14 13 12 11 10 T o o th e r d e v ic e DD 0 .1 m F 0 .1 m F A v= R2 R2R4 R3= R2+R4 R5 = R3+R5 R1+R3 E x a m p le : A v R1 R2 R3 R4 R5 =3 =6 =1 =6 =1 =3 0k 00 0k 50 00 W W kW kW kW C1 X 't a l C2 Note: Xtal = 3.579545MHz crystal C1 = C2 @ 20pF Xtal = 3.58MHz ceramic resonator C1 = C2 @ 39pF Rev. 1.00 8 March 30, 2006 HT9172 Package Information 18-pin DIP (300mil) Outline Dimensions A 18 B 1 10 9 H C D E G F a I Symbol A B C D E F G H I a Dimensions in mil Min. 895 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 915 260 135 145 20 70 3/4 315 375 15 Rev. 1.00 9 March 30, 2006 HT9172 18-pin SOP (300mil) Outline Dimensions 18 A 1 10 B 9 C C' G H D E F a Symbol A B C C D E F G H a Dimensions in mil Min. 394 290 14 447 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 460 104 3/4 3/4 38 12 10 Rev. 1.00 10 March 30, 2006 HT9172 Product Tape and Reel Specifications Reel Dimensions T2 D A B C T1 SOP 18W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2 Rev. 1.00 11 March 30, 2006 HT9172 Carrier Tape Dimensions D E F P0 P1 t W C B0 D1 P K0 A0 SOP 18W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0+0.3 -0.1 16.00.1 1.750.1 11.50.1 1.50.1 1.5+0.25 4.00.1 2.00.1 10.90.1 12.00.1 2.80.1 0.30.05 21.3 Rev. 1.00 12 March 30, 2006 HT9172 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 13 March 30, 2006 |
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